Traditional dual-in-line (DIP) packages are commonly used for semiconductor devices with relatively low input/output (I/O) lead counts. However, in packaging devices with high I/O lead counts, DIPs become impractical. Furthermore, the push in the electronics industry is toward surface mount applications whereas DIPs utilize through-hole technology. The development of leadless pad array carriers has provided some advantages over conventional leaded packages, such as DIPs. These leadless pad array carriers allow greater I/O densities without undue size increases. Additionally, the leadless pad array carriers are surface mount packages which are desirable in today's applications.
The general construction of a leadless pad array carrier includes a semiconductor die mounted on an upper surface of a substrate and a plurality of solder balls attached to a lower surface of the substrate. The existing substrate is a PC board material, such as bismaleimide-triazine (BT) resin clad with copper on both upper and lower surfaces. A complicated manufacturing process is involved to produce the final substrate on which the semiconductor die is mounted. The substrate is processed in panel form and then cut into strips for device assembly.
Starting with an entire panel of copper clad PC board material, through-holes or vias and other necessary holes such as tooling holes are drilled into the panel. Then copper is plated onto the copper cladding and to the sidewalls of the through-holes, forming plated through-holes. The copper plating is achieved by using an electroless plating process followed by an electrolytic plating process. A metal patterning process is performed next, wherein the copper is etched to define the individual patterns of conductive metal traces on both upper and lower surfaces of the panel. The plated through-holes are necessary because they provide the conductive paths between the conductive metal on the upper surface of the substrate to the conductive metal on the lower surface of the substrate.
A pattern of conductive traces for an individual semiconductor die includes bonding posts, routing traces, edge traces, solder pads, and plated through-holes. The bonding posts include the portion of conductive traces that are proximal to the die mounting area and are used in the wire bonding connections between a semiconductor die and the substrate. The edge traces include the portion of the conductive traces that are distal to the die mounting area; or in other words, they are the traces that are located at the edge of the substrate. Edge traces are necessary to route all traces to ground busses located outside of package outlines. This is done to provide common connections for electroplating. Edge traces may be used for probing of assembled devices. Edge traces, however, are not necessarily exposed and may remain covered by solder resist on some devices. Solder pads include the portion of conductive traces located on the lower surface of the substrate where the traces terminate. Solder pads are used for the connection of solder balls to the substrate to provide external electrical connections to the device. Routing traces are merely those portions of the conductive traces that connect the bonding posts to the edge traces and plated through-holes as well as to the solder pads. Electrical continuity is maintained between the traces on the upper and lower surfaces of the substrate through the plated through-holes.
After the etching, a thin film of solder resist is applied over the entire surface area of both upper and lower surfaces of the panel. A resist patterning process is performed next, wherein the solder resist layer is etched away to reveal selective portions of the patterns of conductive metal traces. The portions that are revealed include die mounting areas, the bonding posts, and the edge traces, all of the above being on the upper surface of the panel. Additionally, solder pads on the bottom surface of the panel are also exposed after the patterning of the resist layer. The layer of solder resist serves several purposes. First, the resist prevents solder from running onto the traces during the solder bumping process where solder balls are attached to the solder pads on the lower surface of the substrate. Furthermore, the resist layer provides a uniform and smooth surface for the clamping of the mold die during the molding operation. The exposed portions of the patterns of conductive metal traces are subsequently plated with nickel and gold. The panel is then cut into strips which are then used in the assembly process to manufacture leadless pad array carriers.
FIG. 1 illustrates, in cross section, a completed substrate 10 for a leadless pad array semiconductor device known in the prior art. As illustrated, a PC board material substrate 12 has a pattern of conductive metal traces 14 on both upper and lower surfaces. The pattern of traces 14 has bonding posts 16, edge traces 18, and solder pads 20. Solder pads 20 are all connected to the traces 14 on the upper surface of the substrate, but those connections may not be visible in this cross section plane. Also illustrated are plated through-holes 22. Solder resist 24 is also depicted in FIG. 1, where the solder resist is located on both upper and lower surfaces of the substrate.
FIG. 2 illustrates an assembled leadless pad array carrier 30 in the prior art. As illustrated, a semiconductor die 32 is mounted onto the upper surface of the substrate 10. The die 32 is electrically connected to the bonding posts 16 with a plurality of wire 34 which are bonded to the die 32 and the wire bonding posts 16. The wire bonded semiconductor die is protected with a molded package body 36. Package body 36 is formed by a transfer molding process or a glob top process which overmolds the die 32 and wire bonds 34 with an encapsulating material. After molding, a plurality of solder balls 38 are attached to the solder pads 20 on the bottom surface of the substrate 10. In practice, devices are assembled in strip form and then singulated into individual devices after complete assembly.
One disadvantage to the above described leadless pad array carrier is the complexity of the substrate required. Because the pattern of conductive metal traces are on both the upper and lower surfaces of the substrate, the routing of the traces become complicated. Moreover, the capacitance and inductance of the device are directly proportional to the overall length of the traces. Therefore, it is desired to make the traces as short as possible, which is not always possible with complicated routing of traces. It is also desirable to make the leadless pad array carrier as thin as possible because it is targeted for use in portable equipment such as radios and pagers. Any savings in the overall height of the carrier can have significant benefits.